1. Field of the Invention
The present invention relates generally to metal-oxide-semiconductor field-effect transistors, and more particularly to scaled metal-oxide-semiconductor field-effect transistors (MOSFETs) and their fabrication methods.
2. Description of Related Art
It is well-known that the metal-oxide-semiconductor field-effect transistors (MOSFETs) including an n-channel MOSFET and a p-channel MOSFET in CMOS integrated circuits are scaled down very rapidly, based on the scaling rule in order to gain density *speed-power product. Basically, the surface dimensions of a device including device channel-length and device channel-width can be directly scaled down by using an advanced lithographic technique, and the isolation and contact areas of a device must also be scaled down accordingly in order to increase the packing density of an integrated-circuit. From device physics, the gate-oxide thickness and the source/drain Junction depth are scaled, the lightly-doped drain (LDD) structure is used to reduce the drain-induced barrier lowering (DIBL) and hot-carrier degradation effects, and a deeper channel implant or a pocket (halo) implant using a larger-angle-tilt implantation is used to form the punch-through stop. For a shallow source/drain contact, a barrier-metal layer over a silicided source/drain diffusion region is used. Moreover, the shallow-trench-isolation (STI) instead of the local oxidation of silicon (LOCOS) is used to reduce the isolation area of a device.
Basically, based on the gate structure used in the prior arts, there are polycide-gate land salicide-gate structures. FIG. 1A shows a cross-sectional view of a polycide-gate structure in the channel-length direction, in which a tungsten-silicide layer 103a capping on a doped polycrystalline-silicon layer 102a as a gate metal is formed on a thin gate-dielectric layer 101a; a masking silicon-nitride layer 104a is formed on the tungsten-silicide layer 103a and a silicon-nitride spacer 106a is formed over the sidewalls of the patterned polycide-gate structure; a lightly-doped source/drain diffusion region 105a is formed after patterning the polycide-gate structure and a deeper heavily-doped source/drain diffusion region 107a is formed after forming a silicon-nitride spacer 106a; a self-aligned silicide layer 108a is formed over a deeper heavily-doped source/drain diffusion region 107a. 
FIG. 1B shows a cross-sectional view of a salicide-gate structure in the channel-length direction, in which a polycrystalline-silicon gate layer 102a is formed over a thin gate-dielectric layer 101a; a dielectric spacer (oxide) 106a is formed over the sidewalls of the patterned gate structure; a lightly-doped source/drain diffusion region 105a is formed after patterning the gate structure and a heavily-doped source/drain diffusion region 107a is formed after forming a dielectric spacer 106a; a self-aligned silicide layer 108a, 108b is simultaneously formed over the heavily-doped source/drain diffusion region 107a and the doped polycrystalline-silicon gate layer 102a. Similarly, a silicon-nitride spacer can be used instead of an oxide spacer 106a shown in FIG. 1B, however, the silicon-nitride spacer being deposited on a thin gate-dielectric layer 101a to reduce the stress-induced defects resulting from the silicon-nitride spacer is favorable to eliminate the outdiffusion of boron impurities used to form the lightly-doped source/ drain diffusion region 105a for a p-channel MOSFET.
Apparently, as the thin gate-dielectric layer 110a is scaled to be thinner than 30 Angstroms, the extension length of the lightly-doped source/drain diffusion region 105a shown in FIG. 1A and FIG. 1B becomes a gate leakage path of a scaled MOSFET. Moreover, the overlapping capacitance between the gate and the lightly-doped source/drain diffusion region 105a becomes larger, resulting in lower speed performance. In addition, as the gate length is scaled down below 0.25 xcexcm, the resistance of a narrow gate line becomes higher and the sheet resistance of either polycide gate or salicide gate may also depend on geometries of the gate line due to the agglomeration of the silicide layer, resulting in a higher parasitic resistance for gate interconnection.
FIG. 1C(a) shows a cross-sectional view in the channel-width direction, in which a polycrystalline-silicon gate layer 102a is formed over a flat surface formed by the field-oxides (FOX) and the thin-gate dielectric layer 101a. It is clearly seen that the trench corners of the semiconductor substrate 100 become the field-emission cathode lines for passing the tunneling current from the channel region to the gate 102a. The flat gate layer shown in FIG. 1C(a) is in general good for fine-line lithography of a short-gate length of scaled MOSFETs shown in FIG. 1A and FIG. 1B. FIG. 1C(b) shows that a step between the field-oxides (FOX) and the thin gate-dielectric layer 101a is formed and a polycrystalline-silicon layer 102a is formed over the steps with a non-uniform topography. From FIG. 1C(b), it is clearly seen that the field-emission due to the trench corners can be eliminated, however, a non-uniform topography of the polycrystalline-silicon gate layer is not favorable for fine-line lithography. Moreover, the polycrystalline-silicon gate layer is in general doped by ion-implantation for CMOS fabrication with different doping types for an n-channel MOSFET and a p-channel MOSFET, the non-uniform topography may produce a non-uniform doping depth, resulting in the poly-depletion effect of a scaled MOSFET, especially for a narrow gate-width device.
Based on the above description, there are several issues encountered for a scaled MOSFET. These issues include: (1) high tunneling current between the gate and the source/drain diffusion region through a thin gate-dielectric layer; (2) high parasitic capacitance between the gate and the source/drain diffusion region; (3) high gate-interconnection resistance of a non-planarized conductive gate layer for fine-line lithography; and (4) field-emission through the trench corners of the semiconductor substrate to the gate.
Accordingly, the present invention discloses scaled MOSFETs and their fabrication methods, in which scaled MOSFETs are formed on a flat shallow-trench-isolation structure. The flat shallow-trench-isolation structure includes an active region having a first conductive gate layer formed over a thin gate-dielectric layer and an isolation region being filled with planarized field-oxides. The first conductive gate layer is made of amorphous-silicon or polycrystalline-silicon and is implanted with doping impurities having a dopant type opposite to that of the semiconductor substrate through a first masking dielectric layer. A thin conductive barrier-metal layer is formed over the flat shallow-trench-isolation structure. The thin conductive barrier-metal layer is preferably a refractory metal-nitride layer such as a titanium-nitride layer. For the first group of scaled MOSFETs, a metal layer is formed over the thin conductive barrier-metal layer and a second masking dielectric layer is formed over the metal layer for forming a composite-gate structure. The metal layer is preferably made of a high melting-point metal such as tungsten. Apparently, the conductive barrier-metal layer is used to prevent the interaction between the first conductive gate layer and the metal layer so that a high-conductivity nature of the metal layer can be maintained. For the second group of scaled MOSFETs, a, second conductive gate layer is formed over the conductive barrier-metal layer for forming a salicide-gate structure and is preferably made of polycrystalline-silicon or amorphous-silicon. Similarly, the conductive barrier-metal layer is used to present the agglomeration of the silicide layer during a self-aligned silicidation of the second conductive gate layer.
For the first group of scaled MOSFETs, a stack-layer structure is formed above the flat shallow-trench-isolation structure, which includes a second masking dielectric layer over the metal layer over the conductive barrier-metal layer, is patterned and anisotropically etched to form a gate line. A first dielectric spacer preferably made of silicon-nitrides is formed over the sidewalls of the patterned stack-layer structure to encapsulate the metal layer and also to define the extended length of the first conductive gate layer for both sides of the gate line. The planarized field-oxides in the isolation region are etched back to a depth slightly smaller than a thickness of the first conductive gate layer and then the first conductive gate layer is anisotropically etched either vertically to form a steep-gate structure for the first embodiment of a scaled MOSFET of the present invention or anisotropically to form a taper-gate structure for the second embodiment of a scaled MOSFET of the present invention. A thermal oxidation process is performed to form a first thin poly-oxide layer over the sidewalls of the first conductive gate layer having either a steep-gate structure or a taper-gate structure and a thicker oxide layer over each side portion of the active region having a grade gate-oxide layer near the gate edges of the first conductive gate layer. A shallow moderately-doped source/drain diffusion region is formed in a self-aligned manner by implanting a moderate-dose of doping impurities having a dopant type opposite to that of the semiconductor substrate into each side portion of the active region. Subsequently, a pocket (halo) implant is performed by implanting doping impurities either vertically or with a large-angle-tilt to form the punch-through stops in the semiconductor substrate and the dopant type of the implanted doping impurities is the same as that of the semiconductor substrate. The second dielectric spacer preferably made of silicon-nitrides is formed over the sidewalls of the formed gate structure and, subsequently, a heavily-doped source/drain diffusion region is formed in a self-aligned manner by implanting a high-dose of doping impurities having a dopant type opposite to that of the semiconductor substrate into each side portion of the active region. A rapid thermal annealing process is then performed to redistribute the implanted doping impurities in the semiconductor substrate, and the extension of the shallow moderately-doped source/drain diffusion region is controlled to be extended just under the graded gate-oxide layer for either the steep-gate structure or the taper-gate structure to eliminate or reduce the tunneling current between the first conductive gate layer and the shallow moderately-doped source/drain diffuision region. Apparently, the overlapping capacitance between the first conductive gate layer and the shallow moderately-doped source/drain diffusion region can be much reduced. The thicker oxide layer outside of the second dielectric spacer is then removed by either wet-chemical dip or anisotropic dry etching to form a self-aligned source/drain contact hole and a self-aligned silicide layer is subsequently formed by a well-known self-aligned silicidation process.
For the second group of scaled MOSFETs, a second masking dielectric layer is deposited over the second conductive gate layer, the second conductive gate layer and the conductive barrier-metal layer are patterned by a masking photoresist step to define a gate region of a scaled MOSFET and a gate interconnection and are etched vertically, and the planarized field-oxides in the isolation region are subsequently etched back to a depth slightly smaller than a thickness of the first conductive gate layer and then the first conductive gate layer is anisotropically etched either vertically to form a steep-gate structure for the third embodiment of a scaled MOSFET of the present invention or a taper-gate structure for the fourth embodiment of a scaled MOSFET of the present invention. A thermal oxidation process is performed to form a second thin poly-oxide layer over the sidewalls of the second conductive gate layer, a first thin poly-oxide layer over the sidewalls of the first conductive gate layer for either the steep-gate structure or the taper-gate structure, and a thicker oxide layer over each side portion of the active region having a graded gate-oxide layer formed near the gate edges of the first conductive gate layer. A shallow moderately -doped source/drain diffusion region is formed in a self-aligned manner by implanting a moderate dose of doping impurities hiving a dopant type opposite to that of the semiconductor substrate into each side portion of the active region and also into the second conductive gate layer. Subsequently, a pocket (halo) implant is performed by implanting doping impurities either vertically or with a large-angle-tilt to form the punch-through stops in the semiconductor substrate and the dopant type of the implanted doping impurities is the same as that of the semiconductor substrate, then the second masking dielectric layer is removed. A first dielectric spacer preferably made of silicon-nitrides is formed over he sidewalls of the formed gate structure and, subsequently, a deeper heavily-doped source/drain diffusion region is formed in a self-aligned manner by implanting a high-dose of doping impurities having a dopant type opposite to that of the semiconductor substrate into each side portion of the active region and also into the second conductive gate layer. A rapid thermal annealing process is then performed to redistribute the implanted doping impurities in either the semiconductor substrate or the second conductive gate layer, and the extension of the shallow moderately-doped source/drain diffusion region is controlled to be extended just under the graded gate-oxide layer for either the steep-gate structure or the taper-gate structure to eliminate or reduce the tunneling current between the first conductive gate layer and the shallow moderately-doped source/drain diffusion region. Similarly, the overlapping capacitance between the first conductive gate layer and the shallow moderately-doped source/drain diffusion region can be much reduced. A two-step self-aligned silicidation process is used to completely convert the second conductive gate layer into a thick silicide layer and to form a thin silicide layer over the shallow heavily-doped source/drain diffusion region. Apparently, a high-conductivity gate layer for gate interconnection can be obtained for a scaled MOSFET of the present invention as compared to the salicide gate of the prior arts.